I. Field
The present disclosure relates generally to electronics, and more specifically to techniques for enhancing the slew rate of an active circuit within a feedback circuit, e.g., an integrator within a delta-sigma analog-to-digital converter (ΔΣ ADC).
II. Background
A ΔΣ ADC is commonly used to digitize an analog signal and provide digital samples. The ΔΣ ADC typically includes one or more integrators and one or more feedback paths. Each integrator is often implemented with a switched-capacitor circuit composed of an operational transconductance amplifier (OTA), capacitors, and switches.
High performance ΔΣ ADC often mandates fast settling response for the integrators, especially the first integrator, in the ΔΣ ADC. In many cases, the settling response of an integrator is limited by the slew rate of the OTA. Slew rate is the maximum rate at which an output signal can change due to a large change in an input signal. Faster settling response may be achieved with faster slew rate, which may in turn be obtained with higher bias current for the OTA. There is thus a trade-off between slew rate and power consumption. It is desirable to achieve fast settling response without using high bias current since low power consumption is important in modern wireless and portable electronics devices.